The present invention relates generally a flip-flop circuit and more particularly to a flip-flop circuit of a master slave system that may have a reduced signal propagation delay period from switching a clock signal to providing an output signal so that high-speed operation may be improved.
Recently, the operating frequency of even a CMOS (complementary metal oxide semiconductor) circuit can be required to be in the order of a GHz. In order to satisfy such a high frequency requirement, it has been necessary to improve the operating speed of a flip-flop circuit.
Referring now to FIG. 9, a circuit schematic diagram of a conventional flip-flop circuit is set forth and given the general reference character 900.
Conventional flip-flop circuit 900 has a data input terminal 70, a clock signal input terminal 71 and a data output terminal 72. Conventional flip-flop circuit 900 includes clocked inverters (75, 76, and 77), inverters (78, 79, 80, 81, 82, and 83), a p-channel data transfer gate 73, and an n-channel data transfer gate 74.
Data input terminal 70 is connected to an input of a clocked inverter 75. Clocked inverter 75 has an output connected to an input terminal of inverter 78. Inverter 78 has an output terminal connected to an input terminal of clocked inverter 76 and an input terminal of inverter 79. Clocked inverter 76 has an output terminal connected to an input terminal of inverter 78. Inverter 78 and clocked inverter 76 form a latch. Inverter 81 receives a clock signal at a clock signal input terminal 71 and provides an inverted clock signal CB as an input to inverter 82. Inverter 82 provides a normal clock signal C.
Clocked inverter 75 receives the normal clock signal C at an inverted input terminal and inverted clock signal CB at a normal input terminal. Clocked inverter 76 receives the normal clock signal C at a normal input terminal and inverted clock signal CB at an inverted input terminal.
P-channel data transfer gate 73 has a source/drain terminal connected to an output of inverter 79, another source/drain terminal connected to inputs of inverters (80 and 83), and a control gate connected to receive inverted clock signal CB. N-channel data transfer gate 74 has a source/drain terminal connected to an output of inverter 79, another source/drain terminal connected to inputs of inverters (80 and 83), and a control gate connected to receive normal clock signal C.
Inverter 80 has a output connected to an input of clocked inverter 77. Clocked inverter 77 has an output connected to inputs of inverters (80 and 83). Inverter 80 and clocked inverter 77 form a latch. Clocked inverter 77 receives inverted clock signal CB at a normal input terminal and normal clock signal C at an inverted input terminal.
Inverter 83 has an output connected to data output terminal 72.
In conventional flip-flop circuit 900, data from data input terminal 70 is latched in a latch (master latch) formed by inverter 78 and clocked inverter 76 by the rising edge of a clock signal received at clock signal input terminal 71. At this time, p-channel data transfer gate 73 and n-channel data transfer gate 74 are also turned on (open) by the rising edge of a clock signal received at clock signal input terminal 71. This data is then output at the data output terminal 72 by inverter 83. Based on the falling edge of a clock signal received at clock signal input terminal 71, p-channel data transfer gate 73 and n-channel data transfer gate 74 are also turned off (closed). At this time, clocked inverter 77 is enabled and the data is latched in the latch (slave latch) formed by inverter 80 and clocked inverter 77.
Referring now to FIG. 10, a circuit schematic diagram of a flip-flop circuit is set forth and given the general reference character 1000. Flip-Flop 1000 is proposed to eliminate or reduce a delay of inverters (81 and 82).
Flip-flop circuit 1000 includes the same constituents as conventional flip-flop circuit 900. These same constituents are referred to by the same reference characters.
Flip-flop circuit 1000 differs from conventional flip-flop circuit 900 in that n-channel data transfer gate 74 has a control gate connected directly to the clock signal input terminal 71. By doing so, a delay from the rising edge of a clock signal provided to clock signal input terminal 71 to data being output at data output terminal 72 can be improved by eliminating a delay of inverters (81 and 82) before turning on n-channel data transfer gate 74. Otherwise, the structure of flip-flop circuit 1000 is identical to conventional flip-flop circuit 900.
In conventional flip-flop circuit 900, a timing at which n-channel data transfer gate 74 opens (is turned on) is delayed by a delay (T1+T2 as illustrated in FIG. 2 which will be described later). The delay (T1+T2) corresponds to the propagation delay of inverters (81 and 82). This causes a delay in the change of data at data output terminal 72 with respect to a rising edge of a clock signal input at clock signal input terminal 71.
In flip-flop circuit 1000, a delay can be improved as compared to a delay in conventional flip-flop circuit 900 if a clock signal provided at clock signal input terminal 71 is ideal. However, the clock signal is typically rounded due to capacitance caused by, for example, wire routing or gate loads. The affect of the rounding of the clock signal waveform is illustrated in FIGS. 4 and 5. FIG. 4 is a graph illustrating a relationship between rounding of rising edge of a clock signal waveform and a delay time of data switching from a high to a low logic level at an output of transfer gates. FIG. 5 is a graph illustrating a relationship between rounding of a rising edge of a clock signal waveform and a delay time of data switching from a high to a low logic level at an output of transfer gates. Although the details will be described later, when the waveform of the rising edge of the clock signal waveform is rounded by less than about 1 nanosecond, the delay time in flip-flop circuit 1000 for data switching from a high to a low logic level is less than the delay time in conventional flip-flop circuit 900. However, when the waveform of the rising edge of the clock signal waveform is rounded by more than about 1 nanosecond, the delay time in flip-flop circuit 1000 for data switching from a high to a low logic level is more than the delay time in conventional flip-flop circuit 900.
In this way, if the clock signal is provided directly to n-channel transfer gate 74 as in flip-flop circuit 1000, the delay time improvements deteriorate as the clock signal waveform is rounded. Thus, a speed improvement may only be realized if the clock signal waveform is near ideal. However, a clock signal may be heavily loaded and an ideal waveform may not be feasible.
In view of the above discussion, it would be desirable to provide a flip-flop circuit that may reduce a delay from an edge of a clock signal to an output of a data signal. It would also be desirable to provide a flip-flop circuit where the delay may be reduced even if a clock signal waveform is rounded. In this way, high-speed operations may be improved.
According to the present embodiments, a flip-flop circuit that may have a reduced delay time between an edge of a clock input signal and a data output signal is disclosed. A data signal may be received at a data input terminal, a clock input signal may be received at a clock signal input terminal, and data may be provided at a data output terminal. Data may be transferred from a master latch to a slave latch through a transfer circuit in response to an edge of a clock input signal. A transfer circuit may include a transfer device which may have a control terminal connected to a clock signal input terminal and a transfer device which may have a control terminal connected to a buffered clock signal. In this way, delay time may be reduced while maintaining high-speed operations even if an input clock signal has a rounded or distorted waveform.
According to one aspect of the embodiments, a flip-flop circuit may include a master flip-flop, a slave flip-flop, a data transfer circuit, a first inverter, and a second inverter. The master flip-flop may receive a data input and the slave flip-flop may provide a data output. A data transfer circuit may provide a data path between the master flip-flop and the slave flip-flop. The first inverter may receive a clock signal and provide an inverted clock signal. The second inverter may receive the inverted clock signal and provide a normal clock signal. The data transfer circuit may include a first transfer gate, a second transfer gate, and a third transfer gate. The first transfer gate and the second transfer gate may have a first conductivity type and the third transfer gate may have a second conductivity type. The first, second, and third transfer gates may respectively provide first, second, and third controllable impedance paths between the master flip-flop and the slave flip-flop. The first transfer gate may have a first control terminal connected to receive the clock signal. The second transfer gate may have a second control terminal connected to receive the normal clock signal. The third transfer gate may have a third control terminal connected to receive the inverted clock signal.
According to another aspect of the embodiments, the first conductivity type may be a n-type and the second conductivity type may be a p-type. The first, second, and third transfer gates may be insulated gate field effect transistors (IGFETs).
According to another aspect of the embodiments, the master flip-flop may include a first master flip-flop inverter and a second master flip-flop inverter arranged to form a flip-flop. The slave flip-flop may include a first slave flip-flop inverter and a second slave flip-flop inverter arranged to form a flip-flop.
According to another aspect of the embodiments, the second master flip-flop inverter and the second slave flip-flop inverter may be clocked inverters.
According to another aspect of the embodiments, the first conductivity type may be a p-type and the second conductivity type may be a n-type. The first, second, and third transfer gates may be insulated gate field effect transistors (IGFETs).
According to another aspect of the embodiments, the first, second, and third transfer gates may be IGFETs and the first transfer gate may have a gate width that is less than or equal to a gate width of the second transfer gate.
According to another aspect of the embodiments, a flip-flop circuit may include a master flip-flop, a slave flip-flop, a data transfer circuit, a first inverter, and a second inverter. The master flip-flop may receive a data input and the slave flip-flop may provide a data output. A data transfer circuit may provide a data path between the master flip-flop and the slave flip-flop. The first inverter may receive a clock signal and provide an inverted clock signal. The second inverter may receive the inverted clock signal and provide a normal clock signal. The data transfer circuit may include a first transfer gate, a second transfer gate, and a third transfer gate. The first transfer gate and the second transfer gate may have a first conductivity type and the third transfer gate may have a second conductivity type. The first and second transfer gates may respectively provide first and second controllable impedance paths between a first reference potential and an input of the slave flip-flop. The third transfer gate may provide a third controllable impedance path between a second reference potential and the input of the slave-flip-flop. The first transfer gate may have a first control terminal connected to receive the clock signal. The second transfer gate may have a second control terminal connected to receive the normal clock signal. The third transfer gate may have a third control terminal connected to receive the inverted clock signal.
According to another aspect of the embodiments, the first conductivity type may be a n-type and the second conductivity type may be a p-type. The first, second, and third transfer gates may be insulated gate field effect transistors (IGFETs). The first reference potential may be lower than the second reference potential.
According to another aspect of the embodiments, the first conductivity type may be a p-type and the second conductivity type may be a n-type. The first, second, and third transfer gates may be insulated gate field effect transistors (IGFETs). The first reference potential may be higher than the second reference potential.
According to another aspect of the embodiments, the data transfer circuit may include a fifth transfer gate of the first conductivity type and a sixth transfer gate of the second conductivity type. The fifth and sixth transfer gates may be coupled to receive an output from the master flip-flop at control terminals and may provide a logical inversion when the first, second, and third transfer gates are enabled.
According to another aspect of the embodiments, a flip-flop circuit may include a first inverter, a second inverter, a first data latch, a second data latch, and a transfer circuit. The first inverter may receive a clock signal and provide an inverted clock signal. The second inverter may receive the inverted clock signal and provide a normal clock signal. The first data latch may receive input data and may latch an input data value when the clock signal has a first logic state. The second data latch may receive transfer data and latch a transfer data value when the clock signal has a second logic value. The transfer circuit may receive the input data value and may provide the transfer data when clock signal has the first logic state. The transfer circuit may include a first transfer insulated gate field effect transistor (IGFET) of a first conductivity type, a second IGFET of the first conductivity type, and a third IGFET of a second conductivity type. The first IGFET may have a first IGFET control terminal connected to receive the clock signal. The second IGFET may have a second IGFET control terminal coupled to receive the normal clock signal. The third IGFET may have a third IGFET control terminal coupled to receive the inverted clock signal.
According to another aspect of the embodiments, the first, second, and third IGFETs may have controllable impedance paths connected in parallel between the transfer circuit input and the transfer circuit output.
According to another aspect of the embodiments, the first conductivity type may be n-type and the second conductivity type may be p-type.
According to another aspect of the embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type.
According to another aspect of the embodiments, the first and second IGFETs may have controllable impedance path connected in parallel between a first potential and the transfer circuit output. The third IGFET may have a controllable impedance path connected between a second potential and the transfer circuit output.
According to another aspect of the embodiments, the first conductivity type may be n-type and the second conductivity type may be p-type and the first potential may be a ground potential and the second potential may be a power supply potential.
According to another aspect of the embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type and the first potential may be a power supply potential and the second potential may be a ground potential.